The following description is based on the employment of a CMOS memory so as to characterize the essence of the present invention.
FIG. 1 shows a circuit for a static memory cell of CMOS construction, and FIGS. 2(a), 2(b) and 2(c) respectively show pattern layouts thereof, in which a silicon gate process is employed. In FIG. 1 the reference character Vcc designates a power supply, the reference numeral 20 designates a memory cell. The reference characters T.sub.1 and T.sub.3 designate P-channel field-effect transistors (hereinafter referred to as FET), and T.sub.2 and T.sub.4 designate N-channel FETs, the four FETs constituting a flip-flop. T.sub.5 and T.sub.6 designate N-channel FETs, each constituting a transfer gate. The reference numerals 3 and 4 designate bit lines connected to the sourse or drain of the N-channel FETs T.sub.5 and T.sub.6, respectively. The reference numeral 5 designates a word line connected to the gates of both the FETs T.sub.5 and T.sub.6.
A typical example of the known memory cells will be explained with reference to FIGS. 1 and 2:
For a memory cell pattern layouts by a silicon-gate process using single layer wirings, the following requirements must be satisfied:
(1) The ground line providing the reference potential must be made of aluminum; and
(2) The bit lines must be made of aluminum; on the contrary, if they are made of diffused polysilicon (polycrystalline silicon), the wiring resistance and the load capacity of memory cell increase, which unfavorably affects the operation and the operating speed.
To satisfy these requirements, the bit lines 3, 4 and ground lines 1, 2 are made of aluminum, and arranged in parallel with each other. The word lines 5a, made of polysilicon, are arranged crosswisely of the ground lines 1, 2 and the bit lines 3, 4.
FIGS. 2(a) to 2(c) show pattern layouts for a known memory cell in the order of processing steps. FIG. 2(a) shows a pattern obtained by diffusing impurities into a main surface of the semiconductor substrate so as to produce a diffused region. FIG. 2(b) shows a pattern which is made by adding gates to the pattern of FIG. 2(a). FIG. 2(c) shows a pattern which is made by adding aluminum wirings and contacts to the pattern of FIG. 2(b).
The memory cell pattern of FIG. 2(c) will be explained in comparison with the memory cell circuit shown in FIG. 1:
The ground lines 1, 2 and the bit lines 3, 4, both made of aluminum, are vertically arranged, and the word line 5a, made of polysilicon, is horizontally arranged. There are provided gates 5, and a P-type diffused region 6, which is produced by diffusing impurities into an N-well region 51 formed on the P-type substrate 50. There are provided further diffused regions of N-type, designated by the reference numeral 7. A contact 6a is provided so as to enable an aluminum wiring 61 to be connected to the substrate 50 (i.e. the N-well region 51) and the surface of the diffused region 6 therethrough, thereby applying the power supply Vcc of the N-well region 51 to the diffused region 6. There are provided further contacts 6b which connect between aluminum wirings 62 and the diffused regions 6. In addition, contacts 7a, 6c, 7c and 7b are provided so as to connect between the aluminum wirings 62 and the diffused regions 7, between the aluminum wirings 62 and the gates 5, between the diffused regions 7 and the ground lines 1, 2, and between the diffused regions 7 and the bit lines 3, 4, respectively.
FIG. 3 shows a semiconductor-memory structure using a conventional memory cells. There is provided a memory section 21 including (n+1).sup.2 pieces of memory cells 20, and for this memory section 21, there are provided an X-address decoder 22 and a Y-address decoder 23. A sense circuit 24 is provided for the memory section 21. The reference numerals x.sub.O to x.sub.n and y.sub.O to y.sub.n designate X- and Y-addresses respectively. Under this arrangement the memory section 21 is addressed by the X-decoder 22 and the Y-decoder 23, and the read/write operation of the memory is carried out through the common sense circuit 24.
Under the conventional structure mentioned above, the following problems are likely to arise in accordance with the increase in the memory capacity:
(1) Because the ground lines 1, 2 and the bit lines 3, 4 are made of aluminum, and arranged parallel with each other, the cell area is enlarged, which results in an enlarged chip size. As a result, the productivity is reduced; and
(2) Because the relatively long word lines 5a are made of polysilicon, the wiring resistance and the wiring capacity of the memory cells located remote from the decoders tend to increase, thereby prolonging a signal transfer time accordingly. This unfavourably affects the access speed.
In addition, when the number of the Y-addresses become numerous as shown in FIG. 4, the wiring for data line 14 must be lengthened, which is likely to increase the wiring resistance and the floating capacity to an unnecessary extent. This causes a retarded access speed.